• resistor string
• low-offset
• DAC
• segmented

In the last years sampled data systems have become more popular and dif- fused mainly because of the great amount of operations that a digital system can do with a digital signal. The extremely robust and flexible way of pro- cessing information that is typical of digital systems, acquires relevance if the given output signal can be perceived by a human (or in general if it has an impact into the real world). For this condition to be fulfilled, the digital signal should generally be converted back to the analog domain.
A DAC (Digital to Analog Converter) is an electronic device that converts a digital code into an analog signal that can be in the voltage, current, charge or time (Pulse Width Modulation) domain. It appears as a fundamental block in several circuits, a bridge between digital and analog worlds: audio, video, digital potentiometers, sensors - actuator systems, calibration and motor controls are only a few of the great amount of fields where a digital signal can be needed in its analog form.
This work, that has been carried out at the company NXP Semicon- ductors (Eindhoven, The Netherlands), presents a general purpose single segmented resistor string DAC, designed for a 40nm CMOS technology. A segmented solution allows to achieve the proper resolution with limited area consumption, whereas the resistor string architecture guarantees that the important feature of monotonicity is accomplished with more relaxed re- quirements of components matching accuracy. Since typical loads for these circuits are both capacitive and resistive, in pursuance to obtain the proper driving capability, the output of the resistor string is buffered through an operational amplifier. The latter requires a challenging low offset that is accomplished through a time-continuous dynamic compensation technique (Autozero with feed-forward).
This work is logically separated into 6 Sections. The first three (Section 1, 2 and 3) are preliminary: they explain goals and requirements of DACs, define quantities and parameters used in the field of measurements of these kind of circuits, typical architectures together with their pros and cons.
Section 4 consists in a detailed description of the proposed DAC architecture, starting from its ideal behavior, and then including non-idealities sources.
Section 5 gives importance to the buffer. It reports both an high level and a transistor level analysis, stressing the unlikelihood to achieve the required offset level without taking into account a dynamic compensation. A fre- quency domain description is given and choices in the compensation method are justified.
Section 6 collects simulation results for both the resistor string and the buffer, giving numerical proofs of achievements in terms of proposed specifications.