• Space
• ESA
• Digital Design
• ASIC
• SpaceFibre

In the last few years data rate requirement in on board data handling forspace missions has continuously grown, due to the presence of high resolutioninstruments. This lead the European Space Agency to start working on a new communication standard named SpaceFibre. It is able to fulfil a data rate of 2Gbit/s now and 20Gbit/s in the long run. At the present time an ASIC able to establish a point to point communication does not exists, thus its realisation could be relevant scientifically and economically. In this thesis the complete design process, from the requirements to the FPGA prototyping is performed on one building block of the ASIC: the interface block between a SpaceFibre core, already implemented, and a commercial SERDES. Moreover a preliminary synthesis of the whole chip has been performed. This circuit will be realised on a 65nm Space technology; the preliminary design has been performed on a 65nm commercial technology.