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Archivio digitale delle tesi discusse presso l’Università di Pisa

Tesi etd-05152018-222449


Tipo di tesi
Tesi di laurea magistrale
Autore
TAPPATA, MARCO
URN
etd-05152018-222449
Titolo
Validation through FPGA prototyping of Magneti Marelli Digital Data Diode Concept to improve security in automotive CAN networks
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Prof. Fanucci, Luca
Parole chiave
  • CAN Network
  • cybersecurity
  • automotive
  • FPGA prototyping
  • Validation
Data inizio appello
22/06/2018
Consultabilità
Non consultabile
Data di rilascio
22/06/2088
Riassunto
Due to increasing needs to perform the most advanced functionalities such as the Advanced Driver-Assistance Systems (ADAS) services and the upcoming Vehicle-to-Vehicle (V2V) and Vehicle-to-Infrastructure (V2X) communications, a modern car counts several digital systems (usually called ECUs, Electronic Control Units) which cooperate and communicate each other by means of on-board networks (such as CAN, LIN, MOST, FlexRay) and that are expected to be connected also with external devices (i.e. other cars or external infrastructures), in the near future, by means of wireless networks (e.g. 5G and/or Wi-Fi 802.11p). The wide area of exchanged information on a vehicle, or from a vehicle with the external, provides (and will provide even more), several attack surfaces that can be exploited by hackers to perform cyberattacks on a modern car, as already proved by many demonstrative attacks: one of the most famous is the hack of Jeep Cherokee in the July 2015.
To face this problem, Magneti Marelli in collaboration with the Department of Information Engineering (DII) of University of Pisa, has developed the prototype of an innovative digital firewall for CAN networks, called Digital Data Diode (DDD).
This thesis work focuses on the validation phase of such prototype, by the setting up of a demoboard on the Altera Cyclone V SoC Development Kit board and the development of an automated validation environment written in CAPL and based on the test vectors produced during the testing plan of the DDD.
After a theoretical background on the CAN standard and the analysis of the DDD prototype features, the demoboard has been built synthetizing the DDD IP on the FPGA 5CSXFC6D6F31C6 available on the Altera Cyclone V SoC Development Kit board and connecting the FPGA to a PC by means of Vector VN1630A device, in order to properly stimulate the DDD with specific CAN bit streams and thus verify the respect of the firewall policies specified by the DDD design requirements. During this step it has been necessary to develop also a software tool written in C language, to properly configure the DDD firewall policies by means of its SPI configuration interface.
Then the realization of an automated validation environment which integrated also the software tool for the DDD configuration has been made by means of the CAPL language and the tool CANalyzer of Vector. Such environment was able to automatically set the firewall rules required by a specific test case, stimulate the DDD CAN ports with the expected input test vectors and then to analyze DDD outputs and compare them against the expected outputs, in order to validate the setting up of the demoboard. The importance of this step has been proved when the automated validation environment revealed some bugs within the DDD design.
Finally, after the bugs fixing and the proof of compliance of the DDD demoboard with respect to the DDD design specifications by means of the validation environment, the DDD demoboard was applied to a real case, installing it on a Giulia car by the Italian manufacturer Alfa Romeo.
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