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Archivio digitale delle tesi discusse presso l’Università di Pisa

Tesi etd-04212015-224858


Tipo di tesi
Tesi di laurea magistrale
Autore
CROCETTI, LUCA
URN
etd-04212015-224858
Titolo
Design of an AES-GCM cryptographic core for the IEEE 802.1AE standard
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Carnevale, Berardino
relatore Prof. Fanucci, Luca
Parole chiave
  • 802.1AE
  • AES
  • block ciphers
  • composite field
  • cryptography
  • Ethernet
  • Galois
  • GCM
  • IEEE
  • Karatsuba-Ofman
  • MAC
  • MACsec
  • NIST
  • S-box
  • SecY
Data inizio appello
08/05/2015
Consultabilità
Completa
Riassunto
Nowadays even more IT applications populate the automotive area, thus many internal and external networks can be found on a car. Therefore a modern vehicle is afflicted by the typical IT field security problems. The expected next adoption of Ethernet networks in the automotive area makes suitable the development of a module for the automotive security requirements that is compatible with the Ethernet standard.
This work investigates the services provided by the cryptography in the IT field.
Multiple solutions have been examined and compared to detect the most suitable one for the specific case.
After a deep analysis of the main degrees of freedom in the project workspace, a cryptographic core has been implemented according to the AES and GCM algorithms specifications; this core has been employed to built a security system that was compliant with the IEEE 802.1AE standard and integrated in the Medium Access Control IP of the Renesas Electronics Europe GmbH.
A testing phase has followed to validate the implemented AES-GCM core by an algorithmic point of view: for this purpose the official National Institute of Standards and Technology (NIST) test vectors have been used. Then the compliance with respect to the IEEE 802.1AE standard and the full integration within the MAC IP have been verified.
The realized system has been synthesized both on a FPGA Stratix V of Altera and on a 65 ηm standard-cell ASIC technology: the system shows an occupation of the 5, 01% of the available ALMs on the FPGA (the 16% is employed for registers) and 467 kgates on the standard-cell technology at 125 MHz. The maximum reachable throughput at that frequency is 1 Gbps.
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