• A/D
• ADC
• analog digital converter
• converter
• delta
• SAR
• sigma
• threshold configuring
• wireless

This thesis is inserted in the scenario of innovative, power-efficient analog to digital converter (ADC) architectures for wireless applications. The work is organized into two distinct parts.

The first section focuses on the verification of the performance of a 6-bit 90-nm prototype of a low-power area-efficient successive approximation (SAR) ADC, denoted as "Threshold-Configuring" SAR ADC. Measurements have proven the validity and efficiency of this architecture, making it suitable as a channel converter in a time interleaving system compliant with UWB specifications.

The second section regards a RF Bandpass Delta-Sigma (BP DS) ADC, paving the way towards direct RF sampling receiver architectures: the intent is to move the A/D conversion as close as possible to the antenna, while transfering part of the classical analog signal conditioning to the digital domain. One possible way to meet the stringent dynamic range requirements posed by this approach, is to use a cascaded architecture (Leslie-Singh) to estimate and cancel the in-band portion of the quantization noise introduced by the first stage BP DS ADC.

In this framework, the first stage BP DS ADC has been modeled so as to derive the required nominal digital cancellation filter. A complete mixed-signal model of the Leslie-Singh architecture has then been developed to demonstrate the approach. The work has been extended to incorporate on-line calibration techniques of both the digital filter and of some digitally-tunable analog parameters, such as to accommodate for analog imperfections.