ETD

Archivio digitale delle tesi discusse presso l'Università di Pisa

Tesi etd-04112011-114907


Tipo di tesi
Tesi di laurea specialistica
Autore
DAVALLE, DANIELE
URN
etd-04112011-114907
Titolo
Study and design of the downlink section of a Telemetry, Tracking & Command unit for space applications
Dipartimento
INGEGNERIA
Corso di studi
INGEGNERIA ELETTRONICA
Relatori
relatore Rovini, Massimo
relatore Prof. Fanucci, Luca
Parole chiave
  • ISE
  • Precision
  • Modelsim
  • Mentor Graphics
  • interpolation
  • decimation
  • AWGN
  • Solomon
  • NCO
  • CIC
  • DSP
  • digital signal processing
  • transmitter
  • Reed
  • FIR
  • software defined radio
  • SDR
  • TC
  • TM
Data inizio appello
06/05/2011
Consultabilità
Parziale
Data di rilascio
06/05/2051
Riassunto
This thesis describes the study, design, modeling and implementation of the downlink section of a Telemetry, Tracking & Command (TT&C) unit that has been developed within the framework of STAR project, involving Intecs (Pisa) and Sitael (Pisa). The objective of STAR is the realization of a flexible and in-flight reconfigurable TT&C equipment for Low-Earth-Orbit (LEO) Earth Observation (EO) satellites. The main innovation in STAR is that the transponder is also capable of high speed transmission for scientific data download, resulting in an overall hardware and mass optimization, leading to a considerable cost reduction particularly in the small-satellite scenario.
A State-of-the-Art analysis on present TT&C solutions and EO missions has been carried out as a basis for system requirements definition, in order to have a competitive solution.
The downlink section has been defined in terms of algorithms and architectures and a high-level MATlab model has been developed to validate the system performance also considering the effects of finite-precision arithmetic. The overall performance has been assessed by means of Bit Error Rate (BER) and spectral analysis.
A VHDL description of the transmission chain has been produced, verified and successfully implemented on the Xilinx Space-Grade Virtex-4QV FPGA.
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