ETD

Archivio digitale delle tesi discusse presso l'Università di Pisa

Tesi etd-04092019-175014


Tipo di tesi
Tesi di laurea magistrale
Autore
ZIPPO, RAFFAELE
Indirizzo email
raffaele.zippo@live.it
URN
etd-04092019-175014
Titolo
Study and implementation of a Network Calculus tool for worst case performance on Networks-on-Chip
Dipartimento
INGEGNERIA DELL'INFORMAZIONE
Corso di studi
COMPUTER ENGINEERING
Relatori
relatore Prof. Stea, Giovanni
relatore Ing. Virdis, Antonio
Parole chiave
  • network-on-chip
  • NoC
  • wormhole-routing
  • wormhole-networks
  • network-calculus
Data inizio appello
03/05/2019
Consultabilità
Non consultabile
Data di rilascio
03/05/2089
Riassunto
A Network on Chip is the communication system on an integrated circuit that enables the IP cores to exchange data with each other.

Inspired by large-scale network technologies, they are adapted to different requirements of integrated systems of area coverage, end-to-end delay and bandwidth.
With the diffusion mobile technologies and their increasing requirements of miniaturization and performance, it's increasingly difficult to design ad-hoc NoCs.

Network Calculus is a mathematical framework analysing performance guarantees in computer networks.
While successfully applied for the internet, its models are too simple to represent the NoC routing technologies, in particular wormhole routing, and its congestion issues.

To aid design of NoCs, in this work we show how to model wormhole networks using Network Calculus as a series of FCFS buffers, and how these models were used to develop an integrated tool to study worst-case end-to-end delay on a wormhole network.
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