ETD

Archivio digitale delle tesi discusse presso l'Università di Pisa

Tesi etd-03302012-123425


Tipo di tesi
Tesi di laurea specialistica
Autore
SFRECOLA, MARCO
URN
etd-03302012-123425
Titolo
Large Receive Offload implementation on NetFPGA
Dipartimento
INGEGNERIA
Corso di studi
INGEGNERIA DELLE TELECOMUNICAZIONI
Relatori
relatore Ing. Procissi, Gregorio
relatore Ing. Antichi, Gianni
relatore Prof. Giordano, Stefano
Parole chiave
  • programmable card
  • coalescing
  • verilog
Data inizio appello
23/04/2012
Consultabilità
Non consultabile
Data di rilascio
23/04/2052
Riassunto
The Internet is growing faster and faster. What was originally thought as an interconnection between laboratories engaged in government research, has now been expanded to serve millions of users and a multitude of purposes in all parts of the globe. The latest statistics say the Internet has reached over 30% of the world population, with a growth from 2000 to 2011 of more than 520%. It has changed the way communication, business and entertainment work, and has reshaped the whole world.
The TCP/IP protocol suite has been adopted worldwide as a de-facto standard, and while it has proved successful so far in addressing scalability and routing issues, it requires a growing amount of processing power as the communication speed increases. With each major network speed leap, the bottleneck shifts from network capability to CPU speed.
To face this problem, more and more offloading techniques have been developed and implemented in modern NICs, allowing the CPUs to offload some of the required processing to the underlying hardware. High–speed, simple tasks are better performed in hardware, where memory access is quick and resources are promptly available. Offloading techniques have proved to significantly reduce CPU utilization, leading to improved throughputs and better system performances.
But which features are eligible for an useful and efficient offloading? A lot of different tasks can be run by hardware only. Today, the whole TCP/IP stack can be completely managed by the network card: this is performed by the so–called TOEs (Tcp Offload Engines). These stateful method, though, are known to cause security and support issues by breaking the kernel stack.
In this work, a stateless Large Receive Offload method is presented. LRO consists in aggregating consecutive chunks of data on the receiving side, reducing the number of packets reaching the TCP/IP stack and the amount of work required to the CPU. Where its benefits in terms of sheer performance gain are minor when compared to a TOE, its implementation is completely transparent to the TCP/IP stack, requiring no changes to the kernel behavior. This work shows the implementation of a basic LRO engine on the NetFPGA 1G platform, showing some results in a real file transfer case and in a generated heavy traffic scenario, and providing a starting point for further studies on the offload subject.
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